Typically, an electronic circuit is comprised of a plurality of different sub-circuits, which may be responsible for performing different functions. For example, an integrated circuit is typically constructed of a plurality of individual circuit elements. In such circuitry it is often a requirement to propagate a common signal to the different circuit elements which make up a particular electronic circuit.
In the world of digital circuit design, designers are more often required to create multi-clock designs. Multi-clock implies that a design has at least two clocks, but possibly many more clocks, that are asynchronous. Furthermore, these digital designs will include at least one, though probably multiple signals, across the boundaries between these clock environments. If these signals are not quickly synchronised then the circuit will develop errors.
If one were to consider, for example, an integrated circuit having a plurality of circuit elements, each of which having their own clock, and each having to act on a common signal, then it will be appreciated that it is necessary to adequately synchronise these circuit elements so that the integrated circuit as a whole will not develop any errors.
Systems are known for controlling the transfer of a signal, which is propagated from a first circuit element in a first clocking domain, to a second circuit element in a second clocking domain, and wherein the first and second clocking domains are asynchronous. In the past, one way of handling the asynchronous clock domains was by retiming the signal clocked into the second clock domain, and ensuring that the rate of change and the pulse width (i.e. high/low) is okay between the domains. However, this relies on knowing the rate and the pulse width and so is typically only used for regular timing reference signals. Another way of handling asynchronous clock domains in the past, was by using software to update a register held in each specific clock domain, wherein the registers being accessible via an asynchronous bridge (for example using a known “VALID/ACK” protocol).
However, it is often the case that a signal is transferred from a first clock domain to a plurality of other clock domains which are all asynchronous. In such a situation it will be appreciated that the complexity required for synchronisation is greatly increased.
A known solution to the problem of synchronising one clock domain to many clock domains is to control the timing of the common signal that is passed to the first clock domains. This is accomplished by using so-called hold-off periods, wherein a signal having for example a stream of bits, will send a particular bit and wait for a predetermined time (i.e. x seconds) before the next bit in the stream is transferred to the first clock domain. In such a system it is necessary for the circuit designer to calculate the amount of time necessary for the signal to settle in each of the plurality of clock domains before sending the next signal (i.e. bit in the stream). However, this potentially suffers from a number of disadvantages.
On one hand, if the hand-off time x is selected to be a value which is too big, then the integrated circuit does not operate optimally in that it will have a wasted time period after which all of the clock domains have settled, but during which time the next signal in the signal sequence waits and will not be transferred until the total hand-off time has elapsed. On the other hand, if the hand-off time selected is too small a value, then one or more of the domains will not have settled before the next signal is propagated through the integrated circuit, which results in the worst case scenario in that errors will be introduced into the system.